(1) Field of the Invention
The present invention relates to a plasma display panel and a manufacturing method therefor, and in particular to a method for forming a magnesium oxide protective layer that covers a dielectric layer.
(2) Description of Related Art
A plasma display panel (hereinafter referred to as a “PDP”) is a gas discharge panel in which images are displayed according to phosphor that emits light by being excited by ultraviolet rays generated by gas discharge. PDPs are divided into two types: alternating current (AC) and direct current (DC), depending of the method used to discharge. AC PDPs are the more common type due to their superiority over DC PDPs in terms of luminance, luminous efficiency, and lifespan.
An AC PDP has the following structure. A plurality of electrodes (display electrodes and address electrodes) are arranged on each of two thin sheets of panel glass. The exposed parts of the surface of each sheet of glass and the electrodes are covered by a dielectric layer on which a protective layer (film) is formed. The sheets of glass are positioned and sealed together facing each other via a plurality of barrier ribs, between each pair of which is a phosphor layer. As a result, discharge cells (sub-pixels) are formed in a matrix pattern. Discharge gas is enclosed in the space formed between the two sheets of panel glass.
When the PDP is driven, electricity is supplied appropriately to the plurality of the electrodes based on a field time division gradation display method, in order to obtain discharge in the discharge gas, thereby generating ultraviolet rays that illuminate the phosphor. Specifically, each frame to be displayed is divided into a plurality of subfields, and each subfield is further divided into a plurality of periods. In each frame, first the wall charge of the whole screen is initialized (reset) in an initialization period. Then, in an address period address discharge is performed in order to charge the walls only of cells to be illuminated. Next, in a discharge sustain period an AC voltage (sustain voltage) is applied simultaneously to all discharge cells to obtain sustained discharge for a set period of time. Since discharge in a PDP occurs based on a probability phenomenon, the probability that discharge will occur (called “discharge probability”) varies from cell to cell. Consequently, this characteristic allows the discharge probability of, for example, address discharge to be increased in proportion to the width of the pulse applied to execute address discharge.
An example of a general structure of a PDP is disclosed in Japanese Laid-Open Patent Application No. 9-92133.
Here, the purpose of the protective layer that covers the dielectric layer on the panel glass on the front side of the PDP is to protect the dielectric layer from ion bombardment during discharge, and also to function as a cathode material that contacts the discharge space. As such, it is commonly known that the properties of the protective layer influence discharge characteristics significantly. In the aforementioned document, an MgO material is selected for use as the protective layer because of the fact that firing voltage Vf can be lowered due to the large secondary emission coefficient of MgO, and that MgO is resistant to sputtering. An MgO protective layer is usually formed with a thickness of approximately 0.5 μm to 1 μm by vacuum deposition.
Although MgO is used in the protective layer in a PDP in order lower the firing voltage Vf, the operation voltage is still higher than, for example, a liquid crystal display apparatus, and it is necessary for the transistors and driver ICs used in the driving circuits and the integrated circuits to be highly voltage resistant. This is one factor that contributes to the high cost of PDPs.
More specifically, expectations in recent years for higher definition and larger size of displays has lead to increases in the number of cells, and consequently a need to increase the driving speed of PDPs. Demands are being made to reduce the time assigned to each subframe as a way of shortening driving time. When the driving time is shortened, the discharge probability decreases, and therefore the possibility increases of discharge, such as address discharge, not being performed reliably. One method that attempts to deal with this problem is dual scanning. To achieve dual scanning, the number of data driver ICs in the driving circuit is increased, and address discharge is performed simultaneously from both the top and bottom of the panel towards the center, to achieve what appears to be an address period of a set length of time. However, if this method is employed, the number of data drivers required is twice that of an ordinary PDP and wiring becomes complicated. These factors contribute to high costs and low yield in manufacturing PDPs.
As a result, there is a desire to produce PDPs that consume less power by being driven with low voltage, while controlling the cost of the PDPs.
Examples of techniques for driving of a PDP with low power consumption are disclosed in Japanese Laid-Open Patent Application No. 2001-332175 and Japanese Laid-Open Patent Application No. 10-334809. Such techniques involve creating an energy level in a forbidden band in a vicinity of a conduction band (C.B) by providing an oxygen vacancy defect in the MgO of the protective layer or doping the MgO with impurities. This enables the firing voltage Vf to be lowered, and improves discharge characteristics (in particular, discharge irregularities). FIG. 7 shows the relationship between the energy state of the MgO of the protective layer and the discharge space in the prior art. In the prior art, a first energy level 31 is provided in a vicinity of the conduction band of the protective layer by, for instance, doping the MgO with silicon, as shown in FIG. 7. This increases the number of electrons that are excited in the protective layer during driving, and enables electrons to be supplied to the discharge space more easily, thereby increasing the discharge probability. In FIG. 7, Eg shows the band gap of the MgO, which is 7.8 eV, and Ea shows the electron affinity of the MgO, which is 0.85 eV.
However, the conventional techniques are problematic in that they are unable to both reduce the firing voltage Vf sufficiently and solve display instability called “black noise”. Black noise is a phenomenon where a cell that should be illuminated (a selected cell) is not illuminated, and tends to occur at the boundaries between illuminated areas and non-illuminated areas. Black noise does not occur in all of a plurality of selected cells in one line or one column, but is scattered across the screen. For this reason, black noise is thought to be caused by address discharge either lacking in intensity or failing to occur. This is thought to be caused by the power of the walls to retain charge being reduced, and the effective addressing voltage consequently dropping, if the firing voltage Vf is lowered by simply providing an energy level in a vicinity of the conduction band in the forbidden band of the MgO. As a result, errors occur in addressing, and the image display performance of the PDP is reduced.